1. Field of the Invention
This invention relates generally to the fabrication of etch stops for openings through dielectric layers over fuses for semiconductor devices and more particularly to the uses of an etch stop layer over fuses and a specialized etch process that forms a fuse opening without etch an exposed metal pad.
2. Description of the Prior Art
Fuses can be used to rewire memory and logic circuits. For example, in dynamic or static memory chips, defective memory cells may be replaced by blowing fuses associated with the defective cells, and activating a spare row or column of cells. This circuit rewiring using fusible links allows considerable enhanced yields and reduces the production costs. Also, logic circuits may also be repaired or reconfigured by blowing fuses. For example, it is common to initially fabricate a generic logic chip having a large number of interconnected logic gates. Then, in a final processing step, the chip is customized to perform a desired logic function by disconnecting the unnecessary logic elements by blowing the fuses that connect them to the desired circuitry. Still other applications of laser-blown fuses are possible. There are two methods for blowing fuses: (a) using a laser and (b) passing a high current through the fuse. The portion of the fuse and thin insulating layer which is melted away or "blown" must not deposit or interfere with near-by devices. A laser is often used to break the fuse forming an electrical open by heating the fuse to a high temperature. It is conventional to have an opening through insulating layers over the fuse in the area where the fuse will be broken.
The inventor has found major problems the process of forming opening over fuses. As the number of metal layers and inter metal dielectric (IMD) layers increases, it is more difficult to accurately etch a fuse opening to a precise depth. This etch variability changes the thickness of dielectric layer overlying the fuse. The varying dielectric layer thickness over the fuse reduces the laser fuse cutting rate and yields. Moreover, the additional inter metal dielectric layers, the dielectric layer uniformity within wafer and wafer to wafer create difficulty in accurately etching fuse openings.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering: U.S. Pat. No. 5,292,677 (Dennison) that teaches a reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts. An etch stop layer is deposited on a DRAM wafer after formation of the PMOS and NMOS transistors. U.S. Pat. No. 4,997,789 (Keller) shows an etch stop for a contact plug process. U.S. Pat. No. 5,256,597 (Gambino) shows an etch stop for an interconnect patterning. U.S. Pat. No. 5,536,678 (Peek) shows another etch stop configuration.
However, there still exists a need for an improved etch process with etch stops to form fuse windows through dielectric layers.